Memory devices are subject to a phenomenon known as leakage power. Leakage power is typically dissipated by logic in the periphery and core memory arrays whenever the memory is powered on. As technology continues to shrink device features below sub-nanometer geometries, leakage power dissipation in a memory device increases. This leakage power is becoming a significant factor of the total power dissipation in memory.
One way to reduce leakage power is to reduce the power supply voltage for a memory device. However, the voltage level of a bit cell in the memory needs to be maintained at a minimum voltage specification for retention, while periphery sections of the memory device can operate below the specified voltage. As a result, dual rail memory power supplies have been developed where the periphery and core of a memory operate with different power supplies at different voltages, in an effort to reduce leakage power. Memories with dual rail memory power supplies use level shifters to isolate a high-voltage domain (e.g., VDDM) for one group of circuits from a low-voltage domain (e.g., VDD) for another group of circuits and convert signal voltages by the level shifters to an appropriate domain.